This invention relates to a semiconductor device and, in particular, to a semiconductor device provided with a characteristic checking element for checking electric characteristics.
A semiconductor device is produced through a number of manufacturing processes and shipped to a customer. As a front-end process (diffusion process) of the semiconductor device, a deposition process, a photolithography process, and an impurity diffusion process are repeatedly executed on a semiconductor substrate (sub). Through such a number of processes, a wafer with a plurality of semiconductor devices formed thereon is completed. The wafer thus completed is subjected to a pellet/wafer test process (hereinbelow, will be called a P/W process) in order to verify functions and operations of the semiconductor device formed thereon. Thus, the wafer is judged to be good or defective. Further, as a post-process (assembling process), the wafer is diced to be separated and segmented into individual semiconductor devices. Thereafter, the semiconductor devices are subjected to a packaging process and a final test process and then shipped as products encapsulated or molded in plastic resin or the like.
The semiconductor device is provided with a characteristic checking element for the purpose of evaluating such a number of manufacturing processes. The characteristic checking element is measured or monitored and a result of the measurement is used for review of conditions in each of the manufacturing processes and for analysis of failures or troubles. By checking the characteristic checking element, manufacturing conditions in a semiconductor manufacturer are revealed. This means that the characteristic checking element includes a number of confidential matters of the semiconductor manufacturer. Therefore, the characteristic checking element is generally disposed in a dicing line for separating and segmenting the semiconductor devices on the wafer into individual semiconductor devices. The characteristic checking element disposed in the dicing line is broken during dicing. Therefore, measurement of the characteristic checking element is impossible in a state where the semiconductor device is shipped. Thus, the confidential matters of the semiconductor manufacturer have not been leaked outside.
In recent years, however, in order to further downsize an electronic device, it is often that a customer assembles the semiconductor device into a multi-chip package or the like. In this case, on the side of the customer supplied with the semiconductor device, the semiconductor device is combined with other semiconductor devices and encapsulated or molded in plastic resin to be produced as a commercial product. To such a customer, the semiconductor device in a wafer state is shipped. The characteristic checking element for the semiconductor device shipped in a wafer state is not protected by any means to inhibit easy measurement. Therefore, it is possible to easily measure the characteristic checking element by standing probes onto a measurement pad with their tips in contact therewith.
By analyzing a result of the measurement of the characteristic checking element, it is possible to easily presume or deduce confidential matters regarding semiconductor design and manufacture, such as transistor characteristics and a resistance value of a wiring material. Thus, information regarding the semiconductor design may be leaked to competitors. Thus, a semiconductor manufacturer loses a significant intellectual property in case where characteristics of the semiconductor device manufactured by an advanced process are measured and the information regarding the semiconductor design is leaked outside. The above-mentioned possibility of measurement of the characteristic checking element results in a problem that the semiconductor manufacturer loses its intellectual property and suffers a great loss.
Herein, a wafer provided with the characteristic checking element will be described with reference to FIGS. 1A, 1B, and 1C. FIGS. 1A, 1B, and 1C are a plan view of the wafer, a view showing pad arrangement of the characteristic checking element, and a view showing connection of transistors of the characteristic checking element, respectively. On a wafer 1, dicing lines 3 are arranged in vertical and horizontal directions and a plurality of semiconductor devices 2 are arranged in a matrix fashion. Each of the semiconductor devices 2 has four sides surrounded by the dicing lines 3. At several portions of the dicing lines 3, characteristic checking elements 4, such as transistors or the like, are disposed in order to check characteristics in manufacturing. Each of the characteristic checking elements 4 comprises, for example, three checking transistors 7. The checking transistors 7 have drains (D) connected to individual measurement pads 6, respectively. The checking transistors 7 have gates (G) connected to a common measurement pad 6 and sources (S) connected to another common measurement pad 6.
The semiconductor device 2 has a sub-connection wiring region 11 which is formed at its periphery and provided with a sub-connection wiring 9. Inside the semiconductor device 2, a semiconductor circuit region 10 including a plurality of bonding pads 5 is formed. Each bonding pad 5 serves as a probe pad in a P/W process and also as a connection pad for connection to an external terminal. By standing probes onto the measurement pads 6 for the drains (D), the sources (S), and the gates (G) of the checking transistors 7, characteristics of the checking transistors 7 can be measured. In case where a customer obtains the semiconductor device in such a wafer state, the checking transistors 7 can easily be measured. By analyzing characteristics of the measured transistors, it is possible to easily presume the confidential matters regarding the semiconductor design and manufacture. Thus, there is a problem that information regarding the semiconductor design is leaked to competitors.
As means for inhibiting measurement of the characteristic checking elements of the wafer, there are various methods. For example, it is proposed “to break the elements by laser radiation”, “to physically cut or sever wirings connected to the elements”, “to stand probes on the elements in dicing lines and break them by applying an electric voltage and an electric current”, or the like. However, in each method, the above-mentioned operation must be executed individually for the characteristic checking elements disposed in the wafer. Consequently, a new process is required in order to break the characteristic checking elements. This causes a problem of cost increase.
Characteristic checking elements disposed inside a semiconductor chip and dicing lines are disclosed in the following patent documents. In Japanese Unexamined Patent Application Publication (JP-A) No. 2002-93868, a characteristic checking element is disposed inside a semiconductor chip and a corresponding measurement pad is disposed inside another adjacent semiconductor chip. The characteristic checking element and the measurement pad are connected through a connection wiring across a dicing line. During dicing, the connection wiring between the characteristic checking element and the measurement pad is cut and the characteristic checking element and the measurement pad on the different semiconductor chips are separated to thereby preclude the possibility of subsequent measurement of the characteristic checking element. In Japanese Unexamined Patent Application Publication (JP-A) No. 2005-150514, measurement of a circuit to be inspected is inhibited in response to a signal from a dicing detector. In Japanese Unexamined Patent Application Publication (JP-A) No. 2000-349130, a depletion type transistor is connected between measurement pads of a characteristic checking element. The transistor has a gate connected to a gate potential application pad via a fuse element. By cutting the fuse element, measurement of the characteristic checking element is inhibited.
In Japanese Unexamined Patent Application Publication (JP-A) No. 2006-41236, a measurement pad connected to a bonding pad is disposed in a dicing line. A connection wiring at a boundary between a chip area and the dicing line is arranged as a lower layer so as to prevent the wiring from being peeled off and protruded upward during dicing. In Japanese Unexamined Patent Application Publication (JP-A) No. 2002-217196, interconnections are formed in a dicing line to the vicinity of a distal end of a wafer so as to avoid a characteristic checking element. Thus, a uniform depositing rate of plating is achieved between a center portion and a peripheral portion of the wafer.
In Japanese Unexamined Patent Application Publication (JP-A) No. 2003-332398, a diffusion region of a characteristic checking element in a dicing line is shaded or light-shielded by an aluminum pattern. In Japanese Unexamined Patent Application Publication (JP-A) No. 2005-116606, a measurement pad is formed by a conductive organic film. After inspection, the organic film is removed by using a solvent to thereby inhibit measurement. In Japanese Unexamined Patent Application Publication (JP-A) No. 2004-47535 and Japanese Unexamined Patent Application Publication (JP-A) No. H5-47892, a characteristic checking element is disposed in a dicing line and a measurement pad is disposed inside a chip. However, none of the above-mentioned patent documents describes the problems mentioned above and suggests a solution technology therefor.